1. Field of the Invention
This invention relates to memory systems for use with data busses, and to corresponding integrated circuits, methods and systems.
2. Discussion of the Related Art
Various master-slave type bus architectures are known. One is AMBA (Advanced Micro controller Bus Architecture), designed with three protocols:—ASB: Advanced System Bus—AHB: Advanced High-speed Bus—APB: Advanced Peripheral Bus. AHB was created to address certain shortcomings of ASB. AMBA has a Master which instigates transactions (16 max), a Slave which responds to transactions, and an arbiter which manages bus access according to a designer-defined arbitration scheme (round robin, TDMA, etc.) AHB is notable for having two multiplexed data busses, for using only the rising edge of the clock, and for enabling burst and split transfers. More detailed information can be obtained from the company ARM which developed it. In a multi-master AHB environment, the AHB bus is shared amongst multiple masters. A known example is an arrangement where a processor and a DMA (Direct Memory Access) controller are both coupled to memory via an AHB bus. Both can be masters of the bus. The master with the highest priority has an exclusive access to the bus. It means that during this time, the other masters can be stuck until the bus is freed. The overall efficiency can be reduced.
The present context is an architecture where two AHB masters (a processor and a DMA controller) share the same AHB bus to access a memory. There remains a need for improved arrangements.